ChipScale's wafer level packaging processes are compatible with many fabrication process lines. The packaging processes use low
resolution photomasking, metal evaporation and plating, commercially available polymers, and SMT type stenciling. A major advantage of wafer level packaging is the
ability to combine the front end processing with the typically remote backend processing. This results in reduced total fabrication time and reduced inventory.The Micro SMT®
and Face-up Chip™ packages, when assembled to a circuit, mount the active device "face-up". This feature is important for high frequency applications where shielding the device signals from other circuit elements reduces interference and crosstalk.
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