Company News

Press Releases

Chipscale Licences Microelectronics Component Corporation
Micro Component Corporation, in conjunction with KOA, licenses use of ChipScale's Wafer Level Packaging Technologies

ChipScale Announces the Micro Grid Array
ChipScale announces it's newest member of the Micro SMT® packaging family.

ChipScale Licenses Intarsia Corporation
Intarsia Corporation of San Jose to use Micro SMT® wafer level packaging technology.

ChipScale Alliance Meeting
ChipScale and eight other companies have begun work establishing standard package outlines for Micro SMT® packages

Current Licensees

ChipScale's current licensees include:

Motorola Corporation (Phoenix, AZ)

Mpulse Microwave (San Jose, CA)

Microelectronics Components Corp. (San Jose, CA)

Intarsia Corp. (Fremont CA)

ChipScale Announces License with
Microelectronics Components Corporation.

April 1999 (San Jose) ChipScale, Inc. a leading developer of chip scale and advanced wafer level semiconductor packaging processes announces a license agreement with Microelectronics Components Corporation.

Microelectronics Components Corporation, or MCC is a foundry and supplier of silicon based integrated passive circuits, or IPCs. MCC working in conjunction with its major customers plan to utilize ChipScale's CSP processes to provide IPCs that provide higher performance, smaller size and less cost than current IPCs.

According to Kenny Kumar, MCC's VP of Sales and Marketing, "CSP, such as ChipeScale's Micro SMT® and Face-up Chip™ packaging is a way for us to leapfrog current packaging. Current packaging, at least for IPC suppliers is too large and expensive. It also introduces significant electrical parasitics that affect high frequency performance."

MCC, founded in 1997, lists as its major customers KOA, Vishay and other large passive component suppliers.

MCC's plans are for the implementation of ChipScale's MSMT and Face-up Chip™ wafer level packaging processes in MCC's foundry in San Jose CA. MCC is also planning to implement the process in its foundry in Europe.

For more information contact:

Phil Marcoux at ChipScale, 408-432-1480
Kenny Kumar at MCC, 408-988-3445
Micro SMT® is a registered Trademark of ChipScale, Inc.

CHIPSCALE ANNOUNCES THE MICRO GRID ARRAY

ChipScale announces it's newest member of the Micro SMT® packaging family, the Micro Grid Array™ (MGA). The Micro Grid Array™ uses the Micro SMT® peripheral structure's patented post and beam technology, but in a structure requiring no extra silicon usage.The new structure can be used for both peripheral and array packages and is targeted at those devices that do not require simultaneous top and bottom interconnect, as is required for discrete devices. With this new development, ChipScale clearly establishes itself as the leader in wafer level packaging technology, offering packaging processes that cover the broadest range of packaging needs including discretes, passive components on ceramic, integrated passive components on silicon, and integrated circuits.

The MGA™ process has less processing steps than the standard MSMT structure since it does not require simultaneous top and bottom interconnect. The process can be summarized in the following way:

Deposit epoxy posts.

Apply insulator and open bonding pads.

Create gold beams

Apply insulator and open area on top of posts.

Plate solderable metal or solder balls

The MGA's™ structure is a compliant structure that relies on the compliant beam and epoxy post. The compliant posts are typically .005" in height , but can vary in width and length depending on the application. This allows the MGA™ to have different size posts within a package to accomodate grounds or posts for heat dissipation. The use of the compliant epoxy post and the compliant beam also removes the stress of the solder joint away from the IC, onto the top of the post. This allows the MGA™ to fit into the SMT assembly infrastructure without the need for underfill.

Samples are currently being produced for customers.

The MGA™ has a number of benefits:
Wafer Level Process - Cost Effective
High Performance
Die Size - No Extra Silicon Usage
Can redistribute bonding pads
Variable Post size - Signal / Ground
Compliant post and beam structure - Fits SMT Infrastructure
Heat Sink Capability
Optional Plastic Cap
Wafer Level Probing / Testing

ChipScale will continue to target the low lead count market of less than 68 leads for all of it's structures. While the MGA™ has the potential to handle higher lead counts, because it is a grid array format, ChipScale feels the new structure will help cement it's leadership in the low lead count chip scale market and help drive acceptance across a broad range of products.

Developments will continue on higher lead counts to further broaden ChipScale's acceptance as the wafer level packaging leader. For further information on MGA™ please contact ChipScale at (408) 955-9180 or by fax at (408) 955-9182.

CHIPSCALE, INC. AND INTARSIA CORPORATION
ANNOUNCE LICENSING AGREEMENT

San Jose, California, January 7, 1998……ChipScale, Inc. of San Jose announced a licensing agreement with Intarsia Corporation of San Jose for use of the Micro SMT® wafer level packaging technology. Intarsia will initially utilize the proprietary technology to package thin-film integrated passive components.

"The license with Intarsia is significant," said ChipScale president Jim Young, "in that it represents the first integrated passive component company to license the wafer level technology. The passive market is extremely cost sensitive and this license reflects Intarsia's belief that ChipScale's wafer level packaging technology will provide the means to increase performance while reducing package size and cost.

Intarsia has aggressive plans for the Micro SMT® packaging technology and I believe it will offer them a strategic advantage for their products." "Chip-scale packaging is an enabling technology," said Intarsia CEO Harry Van Wickle, "that will drive a broad industry implementation of integrated passive components. The cost reduction, performance enhancement and size and weight decrease afforded by the Micro SMT® approach is unprecedented in the evolution of electronic packaging. This technology will profoundly strengthen our customer's capability to achieve their product objectives. Intarsia will implement the Micro SMT® process in our manufacturing facility in 1998, as we move quickly to execute a multi-faceted strategy focused on making integrated passives a main stream product."

ChipScale is an engineering, licensing, and development company responsible for development of the Micro SMT® packaging technology. The Micro SMT® packaging technology is unique from the majority of other chip-scale packages in that it is a wafer level process that provides miniaturization in a high performance, low cost structure for low lead count devices. The technology is applicable for integrated circuits, integrated passive components, and discretes.

Intarsia was recently formed by the Dow Chemical Company and Flextronics International Ltd. Intarsia will be able to take advantage of Dow's expertise in materials and Flextronic's commercial capabilities to produce very small, highly integrated passives. Intarsia's roadmap calls for a mix of standard and custom products for a wide range of markets. Harry Van Wickle, the CEO, has over 25 years experience in electronic component manufacturing with an established track record at companies like Texas Instruments, Fairchild Semiconductor, AT&T, Cypress Semiconductor, and Micropolis. Mr. Van Wickle is joined at Intarsia by key personnel from both Dow Chemical Company and Flextronics.

Various Micro SMT® packages compared with conventional wire bond packages

CHIPSCALE ANNOUNCES ALLIANCE MEETING ON PACKAGE
OUTLINE STANDARDIZATION FOR THE MICRO SMT® PACKAGING TECHNOLOGY

San Jose, California, May 12, 1997.... ChipScale, Inc. of San Jose announced that ChipScale and eight other companies have begun work establishing standard package outlines for Micro SMT® packages. The meeting was held at Sun Microsystems and included representatives from Analog Devices; B.I. Technology; Bourns, Inc.; ChipScale, Inc.; IBM; KOA Speer Electronics, Inc.; National Semiconductor; and Sun Microsystems.

The companies met to establish a family of mechanical outlines and footprints with a focus on small lead packages from 6 to 28 leads. Three package outlines were agreed on using established JEDEC / EIAJ outline dimensions. The package outlines included 1608 (0603), 2012 (0805), and 3216 (1206) in both .5mm and .4mm pitch. These outlines and footprints still have to receive approval from JEDEC, but this meeting represents the beginning of a cooperative effort by a number of companies to establish package standards for Micro SMT® technology.

"The companies involved in the meeting are very supportive ," said CEO Phil Marcoux, "and the mix of companies and the type of products they produce reflect the diversity of products the Micro SMT® packaging technology can support."

The Micro SMT® (MSMT) packaging technology is a wafer level packaging process and is part of the evolving family of chip scale packages. MSMT packages are formed using semiconductor fabrication techniques while devices are still in wafer form. The process can produce packages that are die size, with extremely low parasitics, and the ability to use standard SMT processes for attachment to printed circuit boards. ChipScale is a leader in the wafer level chip scale package segment.